In recent years, the manufacturing line for semiconductor devices includes a plurality of units called bays in which treatment apparatuses with the same type of functions are brought together within a vast clean room. A layout that employs a job-shop system has become mainstream. In the job-shop system, the bays are coupled together by a transfer robot and a belt conveyer.
As the workpiece treated in that manufacturing line, a wafer with a large diameter of, for example, 12 inches is used. In the production system, thousands of semiconductor chips are manufactured from one wafer.
However, with this job-shop system, in the case where a plurality of similar treatment processes are repeated, the conveyance within the bay or the conveyance distance between bays significantly increase in length, and the wait time increases. Thus, the manufacturing time increases. This causes a cost increase, for example, causes an increase in work in process. Therefore, the low productivity may become a problem as a manufacturing line for treating a large amount of the workpieces.
Therefore, instead of the conventional manufacturing line in the job-shop system, a manufacturing line in a flow-shop system is also proposed. In this manufacturing line, semiconductor treatment apparatuses are arranged in the order corresponding to the treatment processes.
While this manufacturing line in the flow-shop system is optimal for manufacturing singular products in large quantities, it is necessary to rearrange the location of the respective semiconductor treatment apparatuses in the manufacturing line in the order corresponding to the treatment flow of the workpiece in the case where the manufacturing procedure (recipe) needs to be changed due to a change of products. However, this rearrangement every time the products are changed is not realistic considering labor and time for the rearrangement. Especially, under the circumstances in which huge semiconductor treatment apparatuses are fixedly disposed within the closed space that is the clean room, it is realistically impossible to rearrange the semiconductor treatment apparatuses each time.
Further, in the conventional semiconductor manufacturing systems, because simultaneous productivity (production quantity per unit time) has been emphasized the most as a critical factor in order to minimize manufacturing costs, diameter scale-up in the workpiece size (silicon wafer size) and increase in the manufacturing unit count (number of orders with respect to a single product) have been given priority, pointing to gigantic manufacturing systems, megafab so to say.
In very large-scale manufacturing systems of this sort, the number of processes has exceeded several hundred, and in proportion to that, the number of bays and number of apparatuses has grown considerably.
Accordingly, although for that reason the throughput of the manufacturing lines as a whole has improved, constructing such megafab requires a facilities investment of several billion dollars, making the overall investment cost a huge sum.
Furthermore, along with such manufacturing systems going very large-scale, apparatus control grows complex and conveyance time and wait time in the conveyance system increase significantly. In response to that the number of works in process that dwell along the production line also increases significantly. Since the unit cost of the large-diameter wafers employed here is extraordinarily high, increase in the number of works in process leads to elevation in costs.
Given these and other such circumstances, productivity as a whole, including facilities investment, is said to be turning in a decreasing direction.
Therein, an approach in which the cleanroom is scaled down by means of a local cleaning production system or similar technique is beginning to gain recognition as an expeditious means in order to reduce the facilities investment having grown that huge. This local cleaning is also effective to reduce environmental control costs at the plant.
As a production example in which a local cleaning production system is applied to the entirety of the process stages at a plant, the front-end process of semiconductor integrated circuit manufacture can be given as a unique example as described in Non-Patent Literature 1. In the front-end process of this semiconductor integrated circuit manufacture, the wafers that are products are housed in containers in, and conveyed among, isolated manufacturing apparatuses. The apparatuses are each equipped with a front chamber. The front chambers have two doors. One is between the apparatus main body and the front chamber, and the other is between the front chamber and the exterior. By operating the apparatus such that one or the other of the doors is always shut, the main-body interior is shielded from the exterior at all times. The wafer containers are coupled to the front chambers. In the coupled state, this has the capacity to shield the wafer atmosphere from the exterior at a certain level of performance, enabling the exchange of wafers between the containers and the manufacturing apparatuses.
Lightness, compactness, and simplicity of the mechanisms are demanded of the containers in order to secure ease of conveyance. To fulfill these demands requires ingenuity in the way the containers open and close—in particular, in the way the container doors are housed when the doors are opened. Specifically, a method for housing the container doors within the wafer containers in being coupled with the front chambers must heed the fact that door-housing space becoming necessary will mean running counter to the demands. Given these factors means that for the doors of the wafer containers, being housed into the inside of the front chamber is an appropriate coupling structure. Hewlett-Packard Co. obtained a patent (Patent Literature 1) on a coupling method in which this point is taken into consideration.
The main features with this patent are that there are three subsystems: (1) front chambers, (2) wafer conveyance containers, and (3) there is a wafer transfer mechanism within the front chambers, and that the two doors are combined together and are moved into a clean internal space. The combination of the two doors is due to the following reasons. On the outside surfaces where the two doors contact the exterior containing fine particles, fine particles will cling to each. The combination of the doors traps these fine particles in between the two, and they are housed into the inside of the front chamber, making it possible to prevent diffusion of the fine particles into the local clean environment.
As illustrated in FIG. 1 (a), a container 1 is composed of a container main body 3 and a container door 4, and a front chamber 2, of a front-chamber main body 5 and a front-chamber door 6, with sealing portions provided in three locations: (a) container main body 3—container door 4, (b) front-chamber main body 5—front-chamber door 6, and (c) container main body 3—front-chamber main body 5. The key point with this patent is the sandwiching capture by the two doors for fine particles attached to the door surfaces, but that does not mean that the sandwiched fine particles are eliminated from that region. And countermeasures against the risk of fine particles scattering off the edge surfaces of the sandwiched doors and contaminating the wafers are not taken. Furthermore, since it does not amount to a structure that seals the coupling between the front chamber and with the wafer conveyance container, it lacks function of completely preventing invasion of external wafer contaminating material into the front chamber and into the wafer conveyance container.
Next, Asyst Technologies Inc. patented (Patent Literature 2) an improved mechanism for adding hermeticity to that of the Hewlett-Packard Co. patent, making it practicable for 200-mm wafer systems.
With the Asyst Technologies Inc. patent, as illustrated in FIG. 1(b), the coupled portion consists of four structures, namely, a container (“box”), a container door (“box door”), a front chamber (“port”), and a front-chamber door (“port door”), and is characterized in that among the contacts between these four structures, the four structural intervals (a) container main body 3—container door 4, (b) front-chamber main body 5—front-chamber door 6, (c) container main body 3—front-chamber main body 5, and (d) container door 4—front-chamber door 6 are sealed in order to make them hermetically tight.
Thereafter, given that the sealing system was not perfect, some patents as improvements over the Asyst Inc. patent have been registered. However, the series of improvement patents themselves have given rise to detriment such as follows, complicating the mechanisms, that is, stepped-up manufacturing costs, weight increase, creation of new fine particle generation sources, difficulties with container washing, or similar detriment. Even by means of the improvements in these patents, not only has the gas shield-off not been at a practical level, but also the fine particle shield-off has been imperfect.
Later on, in about the year 2000 the wafer size had become 300-mm, a system separate from Asyst Inc.'s above-described system was proposed, and it became a world standard for 300-mm wafer conveyance systems. This standard system is called the Front-opening Interface Mechanical Standard (FIMS) system, and while being SEMI standards (chiefly SEMI Std. E57, E47.1, E62, and E63), has been patented (Patent Literature 3). FIMS employs a container-door opening that is horizontally directed and a horizontal coupling system.
This is in contradistinction to the vertical coupling with the Asyst system. Further, with the Asyst system, given that the coupling is vertical, the wafers are housed in cassettes inside the containers. The two doors having been combined after coupling are housed inside, and then are moved together with the cassettes into the front chambers. In contrast, with FIMS, the cassettes are omitted. The two doors having been horizontally combined are moved into the front chamber. Then, after the doors subsequently have been lowered in the vertical direction, the wafers within the container are directly taken out to the front chamber using a wafer-transfer robot within the front chamber.
Furthermore, in the FIMS patent, as differing from the Asyst patent, there is no concrete structural definition regarding the sealing structure for the contact portions of the individual structural elements. In actuality, in a practical FIMS system, a structure is rendered in which clearances of about 1 to 2 mm are deliberately provided between the individual structural elements. Specifically, clearances are provided between container—front chamber, and between front chamber—front-chamber doors.
One reason for this is because if a sealing structure that relies on physical contact is provided, mechanical friction is generated in the sealing areas, and that invites large-quantity fine particle generation. But given that the clearances are provided, a drawback that occurs is that hermeticity against gas molecules is lacking in principle.
It should be noted that also in the Asyst system for 200-mm wafers, based on two reasons that are: for reducing the problem of pressure fluctuations that arise within the local environment during the opening/closing of the container doors and front-chamber doors after coupling and the problem of fine particle occurrence caused by air currents stemming due to the pressure fluctuations; and for preventing the container door from becoming difficult to open under negative pressure due to a sealed container, a pressure-relief hole that passes through the exterior is established in the container. These factors result in a structure unable to actually have the shielding performance, in particular, for gas molecules.
What may be understood from the foregoing illustrative antecedent instances is that in sealed-type mechanisms for sealing the individual areas, while it is possible to construct a local cleaning production system with an effective internal/external separation capacity with respect to small molecules such as gases, the downside is that the mechanical friction and the like in the sealing portions produces the side effect of fine particles occurring in numerous amounts. Conversely, if the structure with the clearances is employed, the fine particle generation can be reduced while it is unable to secure the capacity to separate gas molecules internally/externally. This is a shortcoming that the SMIF system has as a self-contradiction. The consequent problem has been that the practical systems cannot avoid the structures with imperfect hermeticity.
Actually, with FIMS systems introduced as the worldwide standard in all semiconductor integrated circuit manufacturing plants handling the latest 300-mm wafers, because they have the clearances, they lack the complete shielding performance not only for gas molecules, but also for particles. As a deleterious effect, although a perfect local cleaning production system originally does not need a clean room because of shielding performance, in all actual plants, the FIMS system still has been introduced within the clean rooms. That is, the current situation is that two kinds of cleaning, by a cleanroom and by local cleaning, have become necessary. This fact has increased facilities investment expenditures and requires high-level control, thus pushing up manufacturing costs significantly.
Thus, downsizing is being tried in the front-end process of semiconductor manufacturing by introducing local cleaning system.
However, this does not go beyond application to manufacturing systems up to now on extended lines, in which simultaneous productivity (production quantity per unit time) has been emphasized the most as a critical factor in order to minimize manufacturing costs. That is, as is typified by the above-described FIMS, diameter scale-up in the workpiece size (silicon wafer size) and increase in the manufacturing unit count (number of orders with respect to a single product) have been given priority, thus still pointing to giant-scaled manufacturing systems, megafab so to say.
FIG. 13 illustrates the effect of size on the semiconductor manufacturing system based on this megafab.
For a cutting-edge semiconductor plant (megafab) in which where the wafer size is 12 inches in the current status, an apparatus count is 300 machines, the number of work in process for wafers that stays in the system is 17,000, the number of masks to be used is 34, and a floor surface area is 20,000 square meters, and the facilities investment total comes to approximately three billion dollars. In this case, the monthly production capacity provides 140 million items per year expressed in terms of 1-cm chips. However, the wafer utilization is less than 1% and the resource usage efficiency is less than 0.1%. Here, as preconditions, assume that the time required by each process (cycle time) is 1 minute/wafer, the process count for semiconductor with eight metallic layers is 500 processes, and the design rule is 90 nm.
Meanwhile, there is the need for manufacturing semiconductor in very small quantities, for example, several pieces to several hundreds of pieces in a manufacturing unit for engineer samples or ubiquitous sensors.
Except this very large-scale manufacturing system, this ultra-small production can be carried out without having to sacrifice cost performance that much. However in a very large-scale manufacturing system, the flow-shop system extremely reduces the cost performance for manufacturing semiconductor in very small quantities in the manufacturing line. Therefore, other kinds of products need to be manufactured in that manufacturing line at the same time.
However, when a wide variety of products are input at the same time for mixed production in that manner, the productivity of the manufacturing line further decreases with increasing number of types of products. As a result, in this very large-scale manufacturing system, very small-quantity production and multiproduct production cannot be appropriately managed.
Conventionally, in a device manufacturing system that employs a flow-shop system or a job-shop system, various measures against drop in utilization in with each system have been proposed (Patent Literature 4 or Patent Literature 5).